1. Field of the Invention
The present invention relates to a system and method for mitigating crosstalk in integrated circuits, and more specifically, aggressor weakening and victim strengthening methods that reduce delay in setup violation cases and increases delay in hold violation cases.
2. Background of the Invention
Crosstalk in related art digital integrated circuits is becoming an increasingly important problem as geometries scale down.
The related art digital integrated circuits experience various problems and disadvantages due to crosstalk. For example, but not by way of limitation, in addition to causing functional failures due to glitching, crosstalk also causes delay changes resulting in both slowdown and speedup of circuit delays depending on the particular interaction of two simultaneously or near simultaneously switching signals.
As process geometries scale down in related art deep submicron processes, the problem of crosstalk is having a significant impact on gate level timing. The related art scaling process introduces closer metal pitches, taller and narrower lines, and accompanying increased operating frequencies, which increase the effects of coupling between lines. The ratio of coupling capacitance to total interconnect capacitance has grown to the point where the portion of interconnect capacitance attributable to coupling can now be as high as 80% for minimum pitch wiring.
Further, the increased coupling in the related art has the disadvantage of increasing crosstalk between wires. Crosstalk can have two substantially negative effects. First, crosstalk results in a functional effect called glitching that results in short pulses on quiet lines adjacent to switching lines. Glitches cause functional errors if they propagate logic level changes to latches.
Second, crosstalk results in a delay effect called dynamic delay (i.e., delay uncertainty), that results in either a slowdown or speedup in circuit delay when signals on adjacent lines switch at a substantially simultaneous time. At a 0.1 micron related art technology, the amount of dynamic delay can be +/xe2x88x9280% of nominal delay. When the effects of dynamic delay are considered in crosstalk aware static timing analysis (STA), setup and hold violations may occur if the aforementioned crosstalk are were not fully recognized in the design process.
Considering the aforementioned related art crosstalk problems, much related art research has been directed at mitigating the crosstalk problems. There has been related art work in crosstalk modeling, calculation of delay change due to crosstalk effects, and crosstalk aware STA. However, the related art work fails to address correcting the aforementioned related art dynamic delay problems of crosstalk.
It is well known in the related art that strengthening victims and weakening aggressors reduces dynamic delay. Commercial vendors refer to xe2x80x9cnoise balancingxe2x80x9d where aggressors with a large xe2x80x9cnoise slackxe2x80x9d (i.e., those aggressors that can absorb weakening without becoming a victim) are weakened, and victims with a small or no noise slack are strengthened.
However, the related art xe2x80x9cblanketxe2x80x9d approach previously described can worsen the dynamic delay problem, because there is no awareness of the critical path in the aforementioned related art technique. Further, delay change effects are significant even when aggressor and victim change relative switching time position with no strength change, which can happen for aggressors or victims on the critical path downstream from the site of strength change. The related art fails to reduce dynamic delay by using the results of crosstalk aware STA to guide dynamic delay reduction.
When signals on related art adjacent coupled lines switch at approximately the same time, there can be a significant effect on the delay of the signal whose driver is at a higher resistance at the time of switching. FIG. 1 illustrates how delays are calculated for an aggressor having an aggressor delay measurement point and a victim having a victim delay measurement point, as well as coupling effects. Victim and aggressor designations apply only to the current switching conditions and are not a permanent characteristic of certain wires. Thus, for different switching conditions, the victim and aggressor designations in FIG. 1 may be interchanged.
The difference in switching time between a victim and aggressor is referred to as skew. Input skew is the difference in switching times at the 50% switching points of victim and aggressor""s input waveforms. The output skew is the difference in the switching times at the 50% switching points of aggressor and victim waveforms, measured at the input to the destination gate, as shown in FIG. 1. When aggressor and victim switch in opposite directions, the victim can be slowed down compared to the case of no proximate aggressor switching (i.e., a quiet aggressor line).
In FIG. 2, the victim is switching high and the aggressor low (i.e., dotted lines). The nominal (i.e., quiet aggressor) victim switching is shown as a dashed line. The solid line shows the case of a proximate switching aggressor, and the jag in the victim waveform shows the effect of slowdown. Since the aggressor is switching low, its lower (stronger) driver is turning on and going to low resistance. On the other hand, the victim""s upper (weaker) driver is turning on. With a relatively strong aggressor and relatively weak victim, the point of maximum slowdown is when the aggressor switches slightly after the victim.
FIG. 3 illustrates the case of the aggressor and victim switching in the same direction. The proximate aggressor switching aids the switching of the victim by effectively removing the effect of some of the coupling capacitance that was slowing down the victim in the nominal case.
Various factors influence the amount of slowdown or speedup, including, but not limited to, the relative sizes of the aggressor and victim drivers, the output skew, the electrical characteristics of the nets involved, the amount of coupling between the nets, and the signal transition times of aggressor and victim (i.e., slew). In static timing analysis (STA), the switching directions of signals are not normally considered. Thus, for calculation of latest arrival time (LAT) in crosstalk aware STA, the signals switch in opposite directions to achieve the worst case switching time. Similarly, for calculation of the earliest arrival time (EAT), the signals switch in the same direction, to achieve the best case switching time.
Related art approaches to STA where coupling between lines is represented by switch factors assume that when there is a possibility of coupling, the worst/best case (i.e., maximum delay for slowdown, or minimum delay for speedup) is used for calculating LAT or EAT. Those related art approaches have the disadvantage of over-constraining the design, and indicating longer clock periods than would be necessary if a more sophisticated analysis were performed. This related art approximation has been used in most recent approaches to crosstalk aware STA.
However, a newer related art approach based on a delay change curve (DCC) has been introduced for timing analysis, but not for crosstalk mitigation. As illustrated in FIG. 4, the related art DCC shows the amount of slowdown or speedup as a function of input skew. Input skew is considered negative if the aggressor switches before the victim, and input skew is zero if the aggressor and the victim switch simultaneously. The DCC curve is generated by fixing the victim and sweeping the aggressor from a large negative to large positive input skew. The range of input skews that cause a slowdown or speedup is referred to as the effective skew window. However, the related art use of the DCC is not for crosstalk mitigation, but only for timing analysis.
The related art DCC is a function of the above-listed parameters that affect slowdown and speedup, and is customized for the particular nets involved. Because there are too many parameters to allow full precharacterization of related art DCC curves, related art partial characterization or related art analytic generation are the only alternatives available in the related art. The generation of the related art curves is not within the scope of the present invention, and given an input skew, aggressor/victim strength, slew rate, the particular nets involved, and the coupling amount, the related art system returns the slowdown or speedup.
Further, the slope characteristics of the related art DCC curves are important. Based on empirical evidence, changes in input skew from large negative skew up to the skew producing the peak of the curve cause a relatively slow change in the rate of slowdown or speedup. As noted above, DCCs are not applied to crosstalk mitigation in the related art.
It is an object of the present invention to overcome at least the problems and disadvantages of the related art.
It is another object of the present invention to overcome the related art dynamic delay aspect of the related art crosstalk problem.
To achieve these and other objects, a method of mitigating crosstalk is provided, comprising (a) generating a timing graph based on static timing analysis and paths having input gates coupled by timing arcs, (b) determining a longest path in said timing graph capable of being shortened, and (c) comparing a length of a selected path to a clock period and setup time. The method also comprises (d) shortening said selected path by strengthening a victim or weakening an aggressor on said selected path if a setup time violation exists for said selected path and if said selected path is capable of being shortened, (e) recalculating said timing graph in accordance with (d), and (f) performing (c) through (e) until no setup time violation exists for said selected path, or said selected path is not capable of further shortening.
Additionally, another method of mitigating crosstalk is provided, comprising (a) generating a timing graph based on static timing analysis and paths having input gates coupled by timing arcs, (b) determining a shortest path in said timing graph capable of lengthening, (c) comparing a clock period and a hold requirement time to a length of a selected path, and (d) shortening said selected path by strengthening said victim or weakening said aggressor on said selected path if a hold requirement time violation exists for said selected path and said selected path is capable of being lengthened. The method further comprises (e) recalculating said timing graph in accordance with (d), wherein (c) through (e) are performed until, and (f) performing (c) through (e) until no holdup requirement time violation exists for said selected path, or said selected path is not capable of further lengthening.
Further, yet another method of mitigating crosstalk is provided, comprising (a) generating a timing graph based on static timing analysis and paths having input gates coupled by timing arcs, (b) determining a longest path in said timing graph capable of being shortened, (c) comparing a length of a selected path to a clock period and a setup time, and (d) shortening said selected path by strengthening a victim or weakening an aggressor on said selected path if a setup time violation exists for said selected path and if said selected path is capable of being shortened. The method also comprises (e) recalculating said timing graph in accordance with (d), (f) performing (c) through (e) until no setup time violation exists for said selected path, or said selected path is not capable of further shortening, (g) determining a shortest path in said timing graph capable of lengthening, and (h) comparing said clock period and a hold requirement time to said length of said selected path. Also, the method comprises (i) shortening said selected path by strengthening said victim or weakening said aggressor on said selected path if a hold requirement time violation exists for said selected path and said selected path is capable of being lengthened, and (j) recalculating said timing graph in accordance with (i), wherein (g) through (j) are performed until no holdup requirement time violation exists for said selected path, or said selected path is not capable of further lengthening.
Further a network having a plurality of input gates coupled by timing arcs is provided, comprising a critical path comprising a first plurality of timing arcs, and a non-critical path comprising a second plurality of timing arcs, wherein crosstalk is mitigated in said network by strengthening a victim thereby making said critical path faster, or weakening an aggressor by delaying said non-critical path.
Additionally, an integrated circuit is provided, comprising a first line having a first signal, and a second line having a second signal, wherein there is substantially simultaneous switching of the said first and said second signal causing crosstalk, and wherein the resulting crosstalk is mitigated by shortening a longest path or lengthening a shortest path.